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Implementacje sprzętowe algorytmów kodowania dla standardów H.264/AVC i JPEG 2000 zostały opisane w następujących publikacjach:

  1. G. Pastuszak, „Sprzętowe implementacje algorytmów kompresji obrazów dla standardu JPEG2000,” Krajowa Konferencja Radiokomunikacji, Radiofonii i Telewizji, str. 341-344, Wrocław, czerwiec 2003.
  2. G. Pastuszak, A. H. Sadka, „A Hardware-Oriented Analysis of the Entropy Coder in H.264/AVC Video Compression Standard, Proceedings of Special VISNET Session at Polish National Conference on Radiocommunications and Broadcasting (KKRRiT 2004), pp. 51-56, Warszawa, June 2004.
  3. G. Pastuszak, “A High-Performance Architecture of Arithmetic Coder in JPEG2000,” CD Proceedings of IEEE International Conference on Multimedia and Expo (ICME’2004), Taipei, Taiwan, June 2004.
  4. G. Pastuszak, “Hardware-Oriented Analysis of the Arithmetic Coding – Comparative Study of JPEG2000 and H.264/AVC Compression Standards,” Proceedings of International Conference on E-business and Telecommunication Networks (ICETE’2004), vol. 3, pp. 309-316, Setubal, Portugal, August 2003.
  5. G. Pastuszak, “A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding,” Proceedings of IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC’04), pp. 303-308, Dresden, Germany, September 2004.
  6. G. Pastuszak, “High-Efficient Architectures of the Context Adaptive Binary Arithmetic Coder for H.264/AVC,” Proceedings of International Workshops on Systems, Signals and Image Processing (IWSSIP’04), pp. 167-170,  Poznań, September 2004.
  7. G. Pastuszak, “High Performance Architectures with the Enhanced Bypass Mode for the Arithmetic Coder in H.264/AVC,” Proceedings of IEE International Conference on Visual Information Engineering (VIE 2005), pp. 367-372, Glasgow, Scotland, UK, April 2005.
  8. G. Pastuszak, “Hardware-Oriented Analysis of the Context Adaptive Binary Arithmetic Coding for Compression of Visual Data,” Proceedings of Special VISNET Session at Polish National Conference on Radiocommunications and Broadcasting (KKRRiT 2005), pp. 61-71, Kraków, June 2005.
  9. G. Pastuszak, A High-Performance Memory Efficient Architecture of the Bit-Plane Coder in JPEG 2000, CD Proceedings of IEEE International Conference on Multimedia and Expo, ICME’2005, Amsterdam, The Netherlands, July 2005.
  10. G. Pastuszak, “Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder,” in International Conference on Image Analysis and Processing, F. Roli and S. Vitulano (eds.), LNCS 3617, Springer, pp. 604-611, 2005.
  11. G. Pastuszak, “A High-Performance Architecture for Embedded Block Coding in JPEG 2000,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 9, pp. 1182-1191 September 2005.
  12. G. Pastuszak and A. H. Sadka, „Architecture Design for the H.264/AVC Binary Coder Based on Arithmetic Coding,” CD Proceedings of Workshop on Immersive Communication and Broadcast Systems (ICOB 2005), Berlin, Germany, October 2005.
  13. G. Pastuszak, “A High-Performance Architecture for EBCOT in the JPEG 2000 Encoder,” Proceedings of IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 693-698, Athens, Greece, November 2005.
  14. G. Pastuszak, “Optymalizacja Architektur Sprzętowych Koderów binarnych dla Standardu H.264/AVC,” VI Seminarium Fundacji Wspierania Rozwoju Radiokomunikacji i Technik Multimedialnych, Warszawa, Grudzień 2005.
  15. G. Pastuszak, „Architecture Design for the Context Formatter in the H.264/AVC Encoder,” Proceedings of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Prague, Czech Republic, April, 2006.
  16. G. Pastuszak, “A Hardware-Oriented Analysis of Arithmetic Coding – Comparative Study of JPEG2000 and H.264/AVC Compression Standards,” Springer, pp. 255-264, 2006.
  17. G. Pastuszak, “Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding,” Proceedings of IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC’06), pp. 380-385, Białystok , Poland , September 2006.
  18. G. Pastuszak, “Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression,” IEEE Workshop on Signal Processing Systems (SIPS’2007), Shanghai, China, 17-19 October, 2007.
  19. G. Pastuszak, “Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection,” IEEE Annual Symposium on VLSI (ISVLSI 2008), Montpellier , France , 7-9 April 2008.
  20. G. Pastuszak, “Architektura transformacji i kwantyzacji w wysoko-przepustowym koderze H.264/AVC opartym na zaawansowanym wyborze trybu kodowania,XI Krajowa Konferencja Naukowa  Reprogramowalne Ukady Cyfrowe, Szczecin , 15 - 16 maj 2008.
  21. G. Pastuszak, “Architektura transformacji i kwantyzacji w wysoko-przepustowym koderze H.264/AVC opartym na zaawansowanym wyborze trybu kodowania,Pomiary Automatyka Kontrola, numer 8, vol. 54, str. 480-482, sierpień 2008.
  22. G. Pastuszak, „A High Performance Architecture of the Double-Mode Binary Coder for H.264.AVC”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 18, no. 7, pp. 949-960, July 2008.

 

Politechnika Warszawska uczestniczy w programie uniwersyteckim firmy Aldec-ADT wykorzystując narzędzia tej firmy w procesie edukacyjnym i badawczym.

 

 

Uwagi, spostrzeżenia:  K.Ignasiak@ire.pw.edu.pl

ostatnia modyfikacja: wrzesień, 2008